A common structure formed during the manufacture of a semiconductor device such as memory, logic, microprocessors, etc., includes a shallow trench isolation structure. This structure can be formed by depositing a dielectric layer 10 such as a tetraethyl orthosilicate glass (TEOS) or borophosphosilicate glass (BPSG) based oxide or other dielectric in a narrow trench 12 in a substrate assembly 14 such as a monocrystalline silicon wafer as shown in FIG. 1. A typical use of this structure is to electrically isolate two adjacent active areas 16. During formation of the structure, for example using chemical vapor deposition (CVD), undesirable impurities such as carbon or unoxidized silicon can be introduced into the dielectric layer. To render the impurities functionally inert, a heating step such as an anneal can be performed to oxidize the impurities and also to anneal the oxide.
As shown in FIG. 2, annealing the dielectric causes it to expand from the addition of molecular oxygen. The original volume of the dielectric layer from FIG. 1 is depicted schematically in FIG. 2 as 20, while the volume after expansion is depicted as 22. Expansion will generally include a volume increase of from about 0.5% to about 5.0%, depending on the dielectric and the amount and composition of undesirable impurities in the dielectric. As the dielectric is annealed the expanding volume of the dielectric layer creates stress gradients 24 at the trench 12 in the substrate assembly 14 under the expanding the dielectric layer and also stresses the dielectric itself, for example along the midline of the trench, which results in difficulties during subsequent processing. For example, the dielectric under stress etches at a different rate than the nonstressed dielectric, as does the stressed substrate assembly when compared to the etch rate of the nonstressed substrate assembly.
A process which has been used to overcome this problem includes forming the dielectric such that it has a variation in its original thickness so that regions under stress are thinner than the nonstressed regions which will etch more quickly. Other processes which have been used to overcome this problem include flowing the dielectric, which requires an undesirably high temperature, and providing special cap layers that protect the dielectric during etching. These can be complicated, inconsistent processes which produce variable results.
A method for forming a dielectric layer which reduces or eliminates the problems described above would be desirable.